The following files were generated for 'chipscope_ila_v1_05_a_0' in directory
D:\Xilinx\Projects\fft_sopc\fft_sopc.srcs\sources_1\ip\chipscope_ila_v1_05_a_0\

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * chipscope_ila_v1_05_a_0_flist.txt

XCO file generator:
   Generate an XCO file for compatibility with legacy flows.

   * chipscope_ila_v1_05_a_0.xco

Creates an implementation netlist:
   Creates an implementation netlist for the IP.

   * chipscope_ila_v1_05_a_0.cdc
   * chipscope_ila_v1_05_a_0.ngc
   * chipscope_ila_v1_05_a_0.v
   * chipscope_ila_v1_05_a_0.veo

Creates an HDL instantiation template:
   Creates an HDL instantiation template for the IP.

   * chipscope_ila_v1_05_a_0.veo

IP Symbol Generator:
   Generate an IP symbol based on the current project options'.

   * chipscope_ila_v1_05_a_0.asy

Generate ISE metadata:
   Create a metadata file for use when including this core in ISE designs

   * chipscope_ila_v1_05_a_0_xmdf.tcl

Generate ISE subproject:
   Create an ISE subproject for use when including this core in ISE designs

   * chipscope_ila_v1_05_a_0.gise
   * chipscope_ila_v1_05_a_0.xise

Deliver Readme:
   Readme file for the IP.

   * chipscope_ila_v1_05_a_0_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * chipscope_ila_v1_05_a_0_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

