//=========================================================
// src/InitDevice.c: generated by Hardware Configurator
//
// This file will be regenerated when saving a document.
// leave the sections inside the "$[...]" comment tags alone
// or they will be overwritten!!
//=========================================================

// USER INCLUDES
#include <SI_EFM8LB1_Register_Enums.h>
#include "InitDevice.h"

// USER PROTOTYPES
// USER FUNCTIONS

// $[Library Includes]
// [Library Includes]$

//==============================================================================
// enter_DefaultMode_from_RESET
//==============================================================================
extern void enter_DefaultMode_from_RESET(void) {
  // $[Config Calls]
  // Save the SFRPAGE
  uint8_t SFRPAGE_save = SFRPAGE;
  WDT_0_enter_DefaultMode_from_RESET();
  PORTS_0_enter_DefaultMode_from_RESET();
  PORTS_1_enter_DefaultMode_from_RESET();
  PBCFG_0_enter_DefaultMode_from_RESET();
  EXTOSC_0_enter_DefaultMode_from_RESET();
  CIP51_0_enter_DefaultMode_from_RESET();
  RSTSRC_0_enter_DefaultMode_from_RESET();
  CLOCK_0_enter_DefaultMode_from_RESET();
  SPI_0_enter_DefaultMode_from_RESET();
  // Restore the SFRPAGE
  SFRPAGE = SFRPAGE_save;
  // [Config Calls]$

}

extern void WDT_0_enter_DefaultMode_from_RESET(void) {
  // $[WDTCN - Watchdog Timer Control]
  SFRPAGE = 0x00;
  //Disable Watchdog with key sequence
  WDTCN = 0xDE; //First key
  WDTCN = 0xAD; //Second key
  // [WDTCN - Watchdog Timer Control]$

}

extern void PORTS_0_enter_DefaultMode_from_RESET(void) {
  // $[P0 - Port 0 Pin Latch]
  // [P0 - Port 0 Pin Latch]$

  // $[P0MDOUT - Port 0 Output Mode]
  // [P0MDOUT - Port 0 Output Mode]$

  // $[P0MDIN - Port 0 Input Mode]
  // [P0MDIN - Port 0 Input Mode]$

  // $[P0SKIP - Port 0 Skip]
  /*
   // P0.0 pin is skipped by the crossbar
   // P0.1 pin is skipped by the crossbar
   // P0.2 pin is skipped by the crossbar
   // P0.3 pin is skipped by the crossbar
   // P0.4 pin is skipped by the crossbar
   // P0.5 pin is skipped by the crossbar
   // P0.6 pin is skipped by the crossbar
   // P0.7 pin is skipped by the crossbar
   */
  P0SKIP = P0SKIP_B0__SKIPPED | P0SKIP_B1__SKIPPED | P0SKIP_B2__SKIPPED
      | P0SKIP_B3__SKIPPED | P0SKIP_B4__SKIPPED | P0SKIP_B5__SKIPPED
      | P0SKIP_B6__SKIPPED | P0SKIP_B7__SKIPPED;
  // [P0SKIP - Port 0 Skip]$

  // $[P0MASK - Port 0 Mask]
  // [P0MASK - Port 0 Mask]$

  // $[P0MAT - Port 0 Match]
  // [P0MAT - Port 0 Match]$

}

extern void PORTS_1_enter_DefaultMode_from_RESET(void) {
  // $[P1 - Port 1 Pin Latch]
  // [P1 - Port 1 Pin Latch]$

  // $[P1MDOUT - Port 1 Output Mode]
  /*
   // P1.0 output is open-drain
   // P1.1 output is open-drain
   // P1.2 output is push-pull
   // P1.3 output is open-drain
   // P1.4 output is push-pull
   // P1.5 output is push-pull
   // P1.6 output is open-drain
   // P1.7 output is open-drain
   */
  P1MDOUT = P1MDOUT_B0__OPEN_DRAIN | P1MDOUT_B1__OPEN_DRAIN
      | P1MDOUT_B2__PUSH_PULL | P1MDOUT_B3__OPEN_DRAIN
      | P1MDOUT_B4__PUSH_PULL | P1MDOUT_B5__PUSH_PULL
      | P1MDOUT_B6__OPEN_DRAIN | P1MDOUT_B7__OPEN_DRAIN;
  // [P1MDOUT - Port 1 Output Mode]$

  // $[P1MDIN - Port 1 Input Mode]
  // [P1MDIN - Port 1 Input Mode]$

  // $[P1SKIP - Port 1 Skip]
  /*
   // P1.0 pin is skipped by the crossbar
   // P1.1 pin is skipped by the crossbar
   // P1.2 pin is not skipped by the crossbar
   // P1.3 pin is not skipped by the crossbar
   // P1.4 pin is not skipped by the crossbar
   // P1.5 pin is not skipped by the crossbar
   // P1.6 pin is not skipped by the crossbar
   // P1.7 pin is not skipped by the crossbar
   */
  P1SKIP = P1SKIP_B0__SKIPPED | P1SKIP_B1__SKIPPED | P1SKIP_B2__NOT_SKIPPED
      | P1SKIP_B3__NOT_SKIPPED | P1SKIP_B4__NOT_SKIPPED
      | P1SKIP_B5__NOT_SKIPPED | P1SKIP_B6__NOT_SKIPPED
      | P1SKIP_B7__NOT_SKIPPED;
  // [P1SKIP - Port 1 Skip]$

  // $[P1MASK - Port 1 Mask]
  // [P1MASK - Port 1 Mask]$

  // $[P1MAT - Port 1 Match]
  // [P1MAT - Port 1 Match]$

}

extern void PBCFG_0_enter_DefaultMode_from_RESET(void) {
  // $[XBR2 - Port I/O Crossbar 2]
  /*
   // Weak Pullups enabled
   // Crossbar enabled
   // UART1 I/O unavailable at Port pin
   // UART1 RTS1 unavailable at Port pin
   // UART1 CTS1 unavailable at Port pin
   */
  XBR2 = XBR2_WEAKPUD__PULL_UPS_ENABLED | XBR2_XBARE__ENABLED
      | XBR2_URT1E__DISABLED | XBR2_URT1RTSE__DISABLED
      | XBR2_URT1CTSE__DISABLED;
  // [XBR2 - Port I/O Crossbar 2]$

  // $[PRTDRV - Port Drive Strength]
  // [PRTDRV - Port Drive Strength]$

  // $[XBR0 - Port I/O Crossbar 0]
  /*
   // UART0 I/O unavailable at Port pin
   // SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4
   //     GPIO pins
   // SMBus 0 I/O unavailable at Port pins
   // CP0 unavailable at Port pin
   // Asynchronous CP0 unavailable at Port pin
   // CP1 unavailable at Port pin
   // Asynchronous CP1 unavailable at Port pin
   // SYSCLK unavailable at Port pin
   */
  XBR0 = XBR0_URT0E__DISABLED | XBR0_SPI0E__ENABLED | XBR0_SMB0E__DISABLED
      | XBR0_CP0E__DISABLED | XBR0_CP0AE__DISABLED | XBR0_CP1E__DISABLED
      | XBR0_CP1AE__DISABLED | XBR0_SYSCKE__DISABLED;
  // [XBR0 - Port I/O Crossbar 0]$

  // $[XBR1 - Port I/O Crossbar 1]
  // [XBR1 - Port I/O Crossbar 1]$

}

extern void EXTOSC_0_enter_DefaultMode_from_RESET(void) {
  // $[Delay counter definition]
  // [Delay counter definition]$

  // $[XOSC0CN - External Oscillator Control]
  /*
   // External CMOS Clock Mode
   */
   XOSC0CN &= ~XOSC0CN_XOSCMD__FMASK;
   XOSC0CN |= XOSC0CN_XOSCMD__CMOS;
  // [XOSC0CN - External Oscillator Control]$
//    SFRPAGE = 0x10;
//    HFOCN = HFOCN_HFO0EN__ENABLED | HFOCN_HFO1EN__ENABLED;

}

extern void SPI_0_enter_DefaultMode_from_RESET(void) {
  // $[SPI0CKR - SPI0 Clock Rate]
  /*
   // SPI0 Clock Rate = 0x01
   */
  //SPI0CKR = (0x01 << SPI0CKR_SPI0CKR__SHIFT);
   SPI0CKR=0;   //Fsck=25 ÌÃö - Òîëüêî íåèçîë
   //SPI0CKR=1;   //Fsck=12.5 ÌÃö Èçîë 4-wire è íåèçîë
   //SPI0CKR=2;   //Fsck=8.33 ÌÃö Èçîë 4-wire è íåèçîë
   //SPI0CKR=3;   //Fsck=6.25 ÌÃö Èçîë 4-wire è íåèçîë
   // SPI0CKR=4;  //Fsck=5 ÌÃö    Èçîë 4-wire è íåèçîë

   // SPI0CKR=5;     //Fsck=4.16 ÌÃö Èçîë 3/4-wire è íåèçîë

   //SPI0CKR_SPI0CKR__SHIFT = 0
  // [SPI0CKR - SPI0 Clock Rate]$
  // fsck = SYSCLK / (2 * (SPI0CKR + 1))=50 MÃö/4=12.5 ÌÃö ïðè SPI0CKR=1
  //                                    =50 ÌÃö/2=25 ÌÃö ïðè SPI0CKR=0
  // $[SPI0FCN0 - SPI0 FIFO Control 0]
  // [SPI0FCN0 - SPI0 FIFO Control 0]$

  // $[SPI0FCN1 - SPI0 FIFO Control 1]
  // [SPI0FCN1 - SPI0 FIFO Control 1]$

//############################################
  SFRPAGE = 0x20;
  SPI0FCN1 &= ~SPI0FCN1_SPIFEN__BMASK;



    SFRPAGE = 0x00;
//#############################################

  // $[SPI0CFG - SPI0 Configuration]
  /*
   // Enable master mode. Operate as a master
   */
  SPI0CFG |= SPI0CFG_MSTEN__MASTER_ENABLED;
  // [SPI0CFG - SPI0 Configuration]$

  // $[SPI0PCF - SPI0 Pin Configuration]
  // [SPI0PCF - SPI0 Pin Configuration]$

  // $[SPI0CN0 - SPI0 Control]
  /*
   // Enable the SPI module
   // 4-Wire Single-Master Mode. NSS is an output and logic high
   */
  SPI0CN0 |= SPI0CN0_SPIEN__ENABLED | SPI0CN0_NSSMD__4_WIRE_MASTER_NSS_HIGH;
  // [SPI0CN0 - SPI0 Control]$

  SPI0CFG = 0x40;
  SPI0CN0 = 0x0d;  //0x01-3wire,0x0d-4wire;
//##################################################3

}

extern void RSTSRC_0_enter_DefaultMode_from_RESET(void) {
  // $[RSTSRC - Reset Source]
  /*
   // A power-on or supply monitor reset occurred
   // A missing clock detector reset occurred
   // A Comparator 0 reset did not occur
   */
  SFRPAGE = 0x00;
  RSTSRC = RSTSRC_PORSF__SET | RSTSRC_MCDRSF__SET | RSTSRC_C0RSEF__NOT_SET;
  // [RSTSRC - Reset Source]$

}

extern void CLOCK_0_enter_DefaultMode_from_RESET(void) {

//################################################
  // $[HFOSC1 Setup]
  // Ensure SYSCLK is > 24 MHz before switching to HFOSC1
//  CLKSEL = CLKSEL_CLKSL__HFOSC0 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
//  while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)  ;
  // [HFOSC1 Setup]$

  // $[CLKSEL - Clock Select]
  /*
   // Clock derived from the Internal High Frequency Oscillator 1
   // SYSCLK is equal to selected clock source divided by 1
   */
//  CLKSEL = CLKSEL_CLKSL__HFOSC1 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
//  while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)  ;
  // [CLKSEL - Clock Select]$
//##################################################
  // $[HFOSC1 Setup]
  // [HFOSC1 Setup]$

  // $[CLKSEL - Clock Select]
  /*
   // Clock derived from the External Oscillator circuit
   // SYSCLK is equal to selected clock source divided by 1
   */
  CLKSEL = CLKSEL_CLKSL__EXTOSC | CLKSEL_CLKDIV__SYSCLK_DIV_1;
  while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY);
  // [CLKSEL - Clock Select]$

}

extern void CIP51_0_enter_DefaultMode_from_RESET(void) {
  // $[PFE0CN - Prefetch Engine Control]
  /*
   // SYSCLK < 75 MHz
   */
  SFRPAGE = 0x10;
  PFE0CN = PFE0CN_FLRT__SYSCLK_BELOW_75_MHZ;
  // [PFE0CN - Prefetch Engine Control]$

}


