C51 COMPILER V9.54   INITDEVICE                                                            04/29/2016 17:53:55 PAGE 1   


C51 COMPILER V9.54, COMPILATION OF MODULE INITDEVICE
OBJECT MODULE PLACED IN .\src\InitDevice.OBJ
COMPILER INVOKED BY: c:\Keil_v5\C51\BIN\C51.exe C:\Keil_v5\Íîâàÿ ïàïêà\myProject_9\src\InitDevice.c OMF2 SMALL DEBUG OBJ
                    -ECTEXTEND ROM(LARGE) WARNINGLEVEL(2) FLOATFUZZY(3) OPTIMIZE(9,SPEED) INTVECTOR(0X0000) INTPROMOTE INCDIR(C:/Keil_v5/Íîâà
                    -ÿ ïàïêà/myProject_9/inc;C:/SiliconLabs/SimplicityStudio/v3/developer/sdks/si8051/v3//Device/shared/si8051Base;C:/Silicon
                    -Labs/SimplicityStudio/v3/developer/sdks/si8051/v3//Device/EFM8LB1;C:/SiliconLabs/SimplicityStudio/v3/developer/sdks/si80
                    -51/v3//Device/EFM8LB1/inc) REGFILE(myProject_9.ORC) PRINT(.\src\InitDevice.lst) COND PAGEWIDTH(120) PAGELENGTH(65) OBJEC
                    -T(.\src\InitDevice.OBJ)

line level    source

   1          //=========================================================
   2          // src/InitDevice.c: generated by Hardware Configurator
   3          //
   4          // This file will be regenerated when saving a document.
   5          // leave the sections inside the "$[...]" comment tags alone
   6          // or they will be overwritten!!
   7          //=========================================================
   8          
   9          // USER INCLUDES
  10          #include <SI_EFM8LB1_Register_Enums.h>
  11          #include "InitDevice.h"
  12          
  13          // USER PROTOTYPES
  14          // USER FUNCTIONS
  15          
  16          // $[Library Includes]
  17          // [Library Includes]$
  18          
  19          //==============================================================================
  20          // enter_DefaultMode_from_RESET
  21          //==============================================================================
  22          extern void enter_DefaultMode_from_RESET(void) {
  23   1        // $[Config Calls]
  24   1        // Save the SFRPAGE
  25   1        uint8_t SFRPAGE_save = SFRPAGE;
  26   1        WDT_0_enter_DefaultMode_from_RESET();
  27   1        PORTS_0_enter_DefaultMode_from_RESET();
  28   1        PORTS_1_enter_DefaultMode_from_RESET();
  29   1        PBCFG_0_enter_DefaultMode_from_RESET();
  30   1        EXTOSC_0_enter_DefaultMode_from_RESET();
  31   1        CIP51_0_enter_DefaultMode_from_RESET();
  32   1        RSTSRC_0_enter_DefaultMode_from_RESET();
  33   1        CLOCK_0_enter_DefaultMode_from_RESET();
  34   1        SPI_0_enter_DefaultMode_from_RESET();
  35   1        // Restore the SFRPAGE
  36   1        SFRPAGE = SFRPAGE_save;
  37   1        // [Config Calls]$
  38   1      
  39   1      }
  40          
  41          extern void WDT_0_enter_DefaultMode_from_RESET(void) {
  42   1        // $[WDTCN - Watchdog Timer Control]
  43   1        SFRPAGE = 0x00;
  44   1        //Disable Watchdog with key sequence
  45   1        WDTCN = 0xDE; //First key
  46   1        WDTCN = 0xAD; //Second key
  47   1        // [WDTCN - Watchdog Timer Control]$
  48   1      
  49   1      }
  50          
  51          extern void PORTS_0_enter_DefaultMode_from_RESET(void) {
C51 COMPILER V9.54   INITDEVICE                                                            04/29/2016 17:53:55 PAGE 2   

  52   1        // $[P0 - Port 0 Pin Latch]
  53   1        // [P0 - Port 0 Pin Latch]$
  54   1      
  55   1        // $[P0MDOUT - Port 0 Output Mode]
  56   1        // [P0MDOUT - Port 0 Output Mode]$
  57   1      
  58   1        // $[P0MDIN - Port 0 Input Mode]
  59   1        // [P0MDIN - Port 0 Input Mode]$
  60   1      
  61   1        // $[P0SKIP - Port 0 Skip]
  62   1        /*
  63   1         // P0.0 pin is skipped by the crossbar
  64   1         // P0.1 pin is skipped by the crossbar
  65   1         // P0.2 pin is skipped by the crossbar
  66   1         // P0.3 pin is skipped by the crossbar
  67   1         // P0.4 pin is skipped by the crossbar
  68   1         // P0.5 pin is skipped by the crossbar
  69   1         // P0.6 pin is skipped by the crossbar
  70   1         // P0.7 pin is skipped by the crossbar
  71   1         */
  72   1        P0SKIP = P0SKIP_B0__SKIPPED | P0SKIP_B1__SKIPPED | P0SKIP_B2__SKIPPED
  73   1            | P0SKIP_B3__SKIPPED | P0SKIP_B4__SKIPPED | P0SKIP_B5__SKIPPED
  74   1            | P0SKIP_B6__SKIPPED | P0SKIP_B7__SKIPPED;
  75   1        // [P0SKIP - Port 0 Skip]$
  76   1      
  77   1        // $[P0MASK - Port 0 Mask]
  78   1        // [P0MASK - Port 0 Mask]$
  79   1      
  80   1        // $[P0MAT - Port 0 Match]
  81   1        // [P0MAT - Port 0 Match]$
  82   1      
  83   1      }
  84          
  85          extern void PORTS_1_enter_DefaultMode_from_RESET(void) {
  86   1        // $[P1 - Port 1 Pin Latch]
  87   1        // [P1 - Port 1 Pin Latch]$
  88   1      
  89   1        // $[P1MDOUT - Port 1 Output Mode]
  90   1        /*
  91   1         // P1.0 output is open-drain
  92   1         // P1.1 output is open-drain
  93   1         // P1.2 output is push-pull
  94   1         // P1.3 output is open-drain
  95   1         // P1.4 output is push-pull
  96   1         // P1.5 output is push-pull
  97   1         // P1.6 output is open-drain
  98   1         // P1.7 output is open-drain
  99   1         */
 100   1        P1MDOUT = P1MDOUT_B0__OPEN_DRAIN | P1MDOUT_B1__OPEN_DRAIN
 101   1            | P1MDOUT_B2__PUSH_PULL | P1MDOUT_B3__OPEN_DRAIN
 102   1            | P1MDOUT_B4__PUSH_PULL | P1MDOUT_B5__PUSH_PULL
 103   1            | P1MDOUT_B6__OPEN_DRAIN | P1MDOUT_B7__OPEN_DRAIN;
 104   1        // [P1MDOUT - Port 1 Output Mode]$
 105   1      
 106   1        // $[P1MDIN - Port 1 Input Mode]
 107   1        // [P1MDIN - Port 1 Input Mode]$
 108   1      
 109   1        // $[P1SKIP - Port 1 Skip]
 110   1        /*
 111   1         // P1.0 pin is skipped by the crossbar
 112   1         // P1.1 pin is skipped by the crossbar
 113   1         // P1.2 pin is not skipped by the crossbar
 114   1         // P1.3 pin is not skipped by the crossbar
C51 COMPILER V9.54   INITDEVICE                                                            04/29/2016 17:53:55 PAGE 3   

 115   1         // P1.4 pin is not skipped by the crossbar
 116   1         // P1.5 pin is not skipped by the crossbar
 117   1         // P1.6 pin is not skipped by the crossbar
 118   1         // P1.7 pin is not skipped by the crossbar
 119   1         */
 120   1        P1SKIP = P1SKIP_B0__SKIPPED | P1SKIP_B1__SKIPPED | P1SKIP_B2__NOT_SKIPPED
 121   1            | P1SKIP_B3__NOT_SKIPPED | P1SKIP_B4__NOT_SKIPPED
 122   1            | P1SKIP_B5__NOT_SKIPPED | P1SKIP_B6__NOT_SKIPPED
 123   1            | P1SKIP_B7__NOT_SKIPPED;
 124   1        // [P1SKIP - Port 1 Skip]$
 125   1      
 126   1        // $[P1MASK - Port 1 Mask]
 127   1        // [P1MASK - Port 1 Mask]$
 128   1      
 129   1        // $[P1MAT - Port 1 Match]
 130   1        // [P1MAT - Port 1 Match]$
 131   1      
 132   1      }
 133          
 134          extern void PBCFG_0_enter_DefaultMode_from_RESET(void) {
 135   1        // $[XBR2 - Port I/O Crossbar 2]
 136   1        /*
 137   1         // Weak Pullups enabled
 138   1         // Crossbar enabled
 139   1         // UART1 I/O unavailable at Port pin
 140   1         // UART1 RTS1 unavailable at Port pin
 141   1         // UART1 CTS1 unavailable at Port pin
 142   1         */
 143   1        XBR2 = XBR2_WEAKPUD__PULL_UPS_ENABLED | XBR2_XBARE__ENABLED
 144   1            | XBR2_URT1E__DISABLED | XBR2_URT1RTSE__DISABLED
 145   1            | XBR2_URT1CTSE__DISABLED;
 146   1        // [XBR2 - Port I/O Crossbar 2]$
 147   1      
 148   1        // $[PRTDRV - Port Drive Strength]
 149   1        // [PRTDRV - Port Drive Strength]$
 150   1      
 151   1        // $[XBR0 - Port I/O Crossbar 0]
 152   1        /*
 153   1         // UART0 I/O unavailable at Port pin
 154   1         // SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4
 155   1         //     GPIO pins
 156   1         // SMBus 0 I/O unavailable at Port pins
 157   1         // CP0 unavailable at Port pin
 158   1         // Asynchronous CP0 unavailable at Port pin
 159   1         // CP1 unavailable at Port pin
 160   1         // Asynchronous CP1 unavailable at Port pin
 161   1         // SYSCLK unavailable at Port pin
 162   1         */
 163   1        XBR0 = XBR0_URT0E__DISABLED | XBR0_SPI0E__ENABLED | XBR0_SMB0E__DISABLED
 164   1            | XBR0_CP0E__DISABLED | XBR0_CP0AE__DISABLED | XBR0_CP1E__DISABLED
 165   1            | XBR0_CP1AE__DISABLED | XBR0_SYSCKE__DISABLED;
 166   1        // [XBR0 - Port I/O Crossbar 0]$
 167   1      
 168   1        // $[XBR1 - Port I/O Crossbar 1]
 169   1        // [XBR1 - Port I/O Crossbar 1]$
 170   1      
 171   1      }
 172          
 173          extern void EXTOSC_0_enter_DefaultMode_from_RESET(void) {
 174   1        // $[Delay counter definition]
 175   1        // [Delay counter definition]$
 176   1      
 177   1        // $[XOSC0CN - External Oscillator Control]
C51 COMPILER V9.54   INITDEVICE                                                            04/29/2016 17:53:55 PAGE 4   

 178   1        /*
 179   1         // External CMOS Clock Mode
 180   1         */
 181   1         XOSC0CN &= ~XOSC0CN_XOSCMD__FMASK;
 182   1         XOSC0CN |= XOSC0CN_XOSCMD__CMOS;
 183   1        // [XOSC0CN - External Oscillator Control]$
 184   1      //              SFRPAGE = 0x10;
 185   1      //              HFOCN = HFOCN_HFO0EN__ENABLED | HFOCN_HFO1EN__ENABLED;
 186   1      
 187   1      }
 188          
 189          extern void SPI_0_enter_DefaultMode_from_RESET(void) {
 190   1        // $[SPI0CKR - SPI0 Clock Rate]
 191   1        /*
 192   1         // SPI0 Clock Rate = 0x01
 193   1         */
 194   1        //SPI0CKR = (0x01 << SPI0CKR_SPI0CKR__SHIFT);
 195   1         SPI0CKR=0;   //Fsck=25 ÌÃö - Òîëüêî íåèçîë
 196   1         //SPI0CKR=1;   //Fsck=12.5 ÌÃö Èçîë 4-wire è íåèçîë
 197   1         //SPI0CKR=2;   //Fsck=8.33 ÌÃö Èçîë 4-wire è íåèçîë
 198   1         //SPI0CKR=3;   //Fsck=6.25 ÌÃö Èçîë 4-wire è íåèçîë
 199   1         // SPI0CKR=4;  //Fsck=5 ÌÃö    Èçîë 4-wire è íåèçîë
 200   1      
 201   1         // SPI0CKR=5;     //Fsck=4.16 ÌÃö Èçîë 3/4-wire è íåèçîë
 202   1      
 203   1         //SPI0CKR_SPI0CKR__SHIFT = 0
 204   1        // [SPI0CKR - SPI0 Clock Rate]$
 205   1        // fsck = SYSCLK / (2 * (SPI0CKR + 1))=50 MÃö/4=12.5 ÌÃö ïðè SPI0CKR=1
 206   1        //                                    =50 ÌÃö/2=25 ÌÃö ïðè SPI0CKR=0
 207   1        // $[SPI0FCN0 - SPI0 FIFO Control 0]
 208   1        // [SPI0FCN0 - SPI0 FIFO Control 0]$
 209   1      
 210   1        // $[SPI0FCN1 - SPI0 FIFO Control 1]
 211   1        // [SPI0FCN1 - SPI0 FIFO Control 1]$
 212   1      
 213   1      //############################################
 214   1              SFRPAGE = 0x20;
 215   1              SPI0FCN1 &= ~SPI0FCN1_SPIFEN__BMASK;
 216   1      
 217   1      
 218   1      
 219   1              SFRPAGE = 0x00;
 220   1      //#############################################
 221   1      
 222   1        // $[SPI0CFG - SPI0 Configuration]
 223   1        /*
 224   1         // Enable master mode. Operate as a master
 225   1         */
 226   1        SPI0CFG |= SPI0CFG_MSTEN__MASTER_ENABLED;
 227   1        // [SPI0CFG - SPI0 Configuration]$
 228   1      
 229   1        // $[SPI0PCF - SPI0 Pin Configuration]
 230   1        // [SPI0PCF - SPI0 Pin Configuration]$
 231   1      
 232   1        // $[SPI0CN0 - SPI0 Control]
 233   1        /*
 234   1         // Enable the SPI module
 235   1         // 4-Wire Single-Master Mode. NSS is an output and logic high
 236   1         */
 237   1        SPI0CN0 |= SPI0CN0_SPIEN__ENABLED | SPI0CN0_NSSMD__4_WIRE_MASTER_NSS_HIGH;
 238   1        // [SPI0CN0 - SPI0 Control]$
 239   1      
 240   1        SPI0CFG = 0x40;
C51 COMPILER V9.54   INITDEVICE                                                            04/29/2016 17:53:55 PAGE 5   

 241   1        SPI0CN0 = 0x0d;  //0x01-3wire,0x0d-4wire;
 242   1      //##################################################3
 243   1      
 244   1      }
 245          
 246          extern void RSTSRC_0_enter_DefaultMode_from_RESET(void) {
 247   1        // $[RSTSRC - Reset Source]
 248   1        /*
 249   1         // A power-on or supply monitor reset occurred
 250   1         // A missing clock detector reset occurred
 251   1         // A Comparator 0 reset did not occur
 252   1         */
 253   1        SFRPAGE = 0x00;
 254   1        RSTSRC = RSTSRC_PORSF__SET | RSTSRC_MCDRSF__SET | RSTSRC_C0RSEF__NOT_SET;
 255   1        // [RSTSRC - Reset Source]$
 256   1      
 257   1      }
 258          
 259          extern void CLOCK_0_enter_DefaultMode_from_RESET(void) {
 260   1      
 261   1      //################################################
 262   1              // $[HFOSC1 Setup]
 263   1              // Ensure SYSCLK is > 24 MHz before switching to HFOSC1
 264   1      //      CLKSEL = CLKSEL_CLKSL__HFOSC0 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
 265   1      //      while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)     ;
 266   1              // [HFOSC1 Setup]$
 267   1      
 268   1              // $[CLKSEL - Clock Select]
 269   1              /*
 270   1               // Clock derived from the Internal High Frequency Oscillator 1
 271   1               // SYSCLK is equal to selected clock source divided by 1
 272   1               */
 273   1      //      CLKSEL = CLKSEL_CLKSL__HFOSC1 | CLKSEL_CLKDIV__SYSCLK_DIV_1;
 274   1      //      while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY)     ;
 275   1              // [CLKSEL - Clock Select]$
 276   1      //##################################################
 277   1        // $[HFOSC1 Setup]
 278   1        // [HFOSC1 Setup]$
 279   1      
 280   1        // $[CLKSEL - Clock Select]
 281   1        /*
 282   1         // Clock derived from the External Oscillator circuit
 283   1         // SYSCLK is equal to selected clock source divided by 1
 284   1         */
 285   1        CLKSEL = CLKSEL_CLKSL__EXTOSC | CLKSEL_CLKDIV__SYSCLK_DIV_1;
 286   1        while ((CLKSEL & CLKSEL_DIVRDY__BMASK) == CLKSEL_DIVRDY__NOT_READY);
 287   1        // [CLKSEL - Clock Select]$
 288   1      
 289   1      }
 290          
 291          extern void CIP51_0_enter_DefaultMode_from_RESET(void) {
 292   1        // $[PFE0CN - Prefetch Engine Control]
 293   1        /*
 294   1         // SYSCLK < 75 MHz
 295   1         */
 296   1        SFRPAGE = 0x10;
 297   1        PFE0CN = PFE0CN_FLRT__SYSCLK_BELOW_75_MHZ;
 298   1        // [PFE0CN - Prefetch Engine Control]$
 299   1      
 300   1      }
 301          
 302          
 303          
C51 COMPILER V9.54   INITDEVICE                                                            04/29/2016 17:53:55 PAGE 6   

 304          //extern void HFOSC_0_enter_DefaultMode_from_RESET(void) {
 305          
 306                  // $[HFOCN - High Frequency Oscillator Control]
 307                  /*
 308                   // Force High Frequency Oscillator 0 to run
 309                   // Force High Frequency Oscillator 1 to run
 310                   */
 311          //      SFRPAGE = 0x10;
 312          //      HFOCN = HFOCN_HFO0EN__ENABLED | HFOCN_HFO1EN__ENABLED;
 313                  // [HFOCN - High Frequency Oscillator Control]$
 314          
 315          //}
 316          


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    116    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----       1
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
   EDATA SIZE       =   ----    ----
   HDATA SIZE       =   ----    ----
   XDATA CONST SIZE =   ----    ----
   FAR CONST SIZE   =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)
